(1) Field of the Invention
The present invention relates to a method of fabricating metal oxide semiconductor field effect transistors, (MOSFET), and more specifically to a process used to improve the yield and performance of the MOSFET devices.
(2) Description of the Prior Art
The semiconductor industry is continually striving to improve device performance while still maintaining, or even decreasing, the cost of the semiconductor product. These objectives have been partially satisfied by the ability of the industry to create smaller semiconductor devices, thus enabling more semiconductor chips to be realized from a starting substrate, thus reducing the processing cost for a specific semiconductor chip. The ability to fabricate devices, with sub-micron features, has been the main contributor in obtaining smaller chips, with the smaller chips still possessing a level of integration, equal to the integration achieved with larger counterparts. In addition to satisfying the cost objectives, the use of sub-micron features, or micro-miniaturization, has also resulted in performance increases, resulting from the decreased capacitances and resistances, realized from the smaller dimensions.
However even with the use of micro-miniaturization, semiconductor engineering is still striving for additional methods to further improve device performance and yield. For example Liang, et al, in U.S. Pat No. 5,614,430, describe a MOSFET device in which an anti-punchthrough region is formed in a sub-half micron channel length region, featuring the self-alignment of the anti-punchthrough region, to an overlying polysilicon gate structure. This procedure allows the parasitic capacitance, realized from the anti-punchthrough region, to be minimized, or confined to only the region directly below the polysilicon gate. The present invention will also address the self-alignment of a channel region to an overlying gate structure. However this invention will also describe a process in which the self-aligned channel region is created after the formation of ion implanted source and drain regions. This sequence allows the annealing of source and drain regions to be performed, removing ion implant damage, without redistribution of the channel region dopants. The sensitive channel region dopants, used for threshold voltage adjustments, as well as anti-punchthrough purposes, are subsequently created, and subjected to a minimum of high temperature procedures, thus maintaining the preferred location of these sensitive regions.